Circuit Design 03

Understanding VHDL Data Types: A Comprehensive Guide #

When learning VHDL for hardware design, understanding data types is essential for writing efficient code. Data types define the kind of information your signals can carry and what operations you can perform on them. This guide explores VHDL data types in detail, helping you understand how to use them effectively in your designs.

VHDL Objects #

Before diving into data types, let’s understand the VHDL objects that use them. VHDL has four basic objects:

CONSTANT: As the name suggests, these objects hold values that cannot be changed during execution. They’re declared with the := operator and are useful for parameters that remain fixed throughout your design.

CONSTANT bits: INTEGER := 16;
CONSTANT flag: BIT := '1';
CONSTANT mask: BIT_VECTOR(1 TO 8) := "00001111";

SIGNAL: These represent the physical wires and interconnections in your circuit. All ports in an entity are signals by default. Signals are updated only after the completion of the process or subprogram where they’re assigned.

SIGNAL enable: BIT := '0';
SIGNAL byte: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL count: NATURAL RANGE 0 TO 255;

VARIABLE: Unlike signals, variables are local to processes or subprograms and are updated immediately. They’re useful for intermediate calculations within sequential code.

VARIABLE flip: STD_LOGIC := '1';
VARIABLE address: STD_LOGIC_VECTOR(0 TO 15);
VARIABLE counter: INTEGER RANGE 0 TO 127;

FILE: Used primarily for simulation purposes, file objects allow reading from and writing to files.

The key difference between SIGNAL and VARIABLE is that signals model hardware connections with delayed updates, while variables provide immediate updates for local computations.

Data Type Libraries and Packages #

VHDL organizes data types into libraries and packages. The most important ones include:

  • Package standard: Defines basic types like BIT, INTEGER, BOOLEAN
  • Package std_logic_1164: Defines the industry-standard STD_LOGIC types
  • Package numeric_std: Provides UNSIGNED and SIGNED types with arithmetic operations
  • Package numeric_bit: Similar to numeric_std but uses BIT as the base type
  • Packages fixed_pkg and float_pkg: Support fixed-point and floating-point arithmetic

VHDL Data Type Classifications #

VHDL data types can be classified in several ways:

  1. By source of declaration:

    • Predefined types (built into VHDL libraries)
    • User-defined types (created for specific needs)

  2. By nature of elements:

    • Numeric types (INTEGER, fixed-point, floating-point)
    • Enumerated types (explicitly listed values like BIT)

  3. By number of values:

    • Scalar types (single values)
    • Composite types (collections: arrays and records)

  4. By number of bits (from a hardware perspective):

    • Scalar (single bit, like ‘1’)
    • 1D array (bit vector, like “01000”)
    • 1D×1D array (pile of bit vectors)
    • 2D array (matrix of bits)
    • More complex structures (3D arrays, etc.)

Standard Data Types #

The package standard defines several essential types:

BIT and BIT_VECTOR: The simplest binary type with only two possible values: ‘0’ and ‘1’.

TYPE BIT IS ('0', '1');
TYPE BIT_VECTOR IS ARRAY (NATURAL RANGE <>) OF BIT;

BOOLEAN: Another two-value type used for conditions.

TYPE BOOLEAN IS (FALSE, TRUE);

INTEGER, NATURAL, POSITIVE: Whole number types with different ranges.

TYPE INTEGER IS RANGE -2147483647 TO 2147483647;
SUBTYPE NATURAL IS INTEGER RANGE 0 TO INTEGER'HIGH;
SUBTYPE POSITIVE IS INTEGER RANGE 1 TO INTEGER'HIGH;

CHARACTER and STRING: For text representation.

Standard-Logic Data Types #

The industry standard for hardware design uses STD_LOGIC and STD_LOGIC_VECTOR from the std_logic_1164 package. Unlike BIT, STD_LOGIC has nine possible values:

TYPE STD_ULOGIC IS ('U','X','0','1','Z','W','L','H','-');

Where:

  • ‘U’: Uninitialized
  • ‘X’: Forcing unknown
  • ‘0’: Forcing low
  • ‘1’: Forcing high
  • ‘Z’: High impedance (for tri-state buffers)
  • ‘W’: Weak unknown
  • ‘L’: Weak low
  • ‘H’: Weak high
  • ‘-’: Don’t care (for optimization)

The vector form is defined as:

TYPE STD_LOGIC_VECTOR IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC;

STD_LOGIC is a “resolved” type, meaning it handles situations where multiple drivers connect to a single signal (like in tri-state buses).

Unsigned and Signed Data Types #

For performing arithmetic operations, VHDL provides UNSIGNED and SIGNED types. These are defined in packages like numeric_std:

TYPE UNSIGNED IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC;
TYPE SIGNED IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC;

UNSIGNED values range from 0 to 2^N-1, while SIGNED values (using two’s complement representation) range from -2^(N-1) to 2^(N-1)-1, where N is the number of bits.

Fixed and Floating-Point Types #

VHDL 2008 introduced better support for fixed and floating-point arithmetic with types:

TYPE UFIXED IS ARRAY (INTEGER RANGE <>) OF STD_LOGIC; --unsigned fixed-point
TYPE SFIXED IS ARRAY (INTEGER RANGE <>) OF STD_LOGIC; --signed fixed-point
TYPE FLOAT IS ARRAY (INTEGER RANGE <>) OF STD_LOGIC; --floating-point

These types allow specification of a decimal point location and support fractional numbers.

User-Defined Types #

VHDL allows you to create your own data types for specific needs:

Integer Types:

TYPE temperature IS RANGE 0 TO 273;
TYPE my_integer IS RANGE -32 TO 32;

Enumerated Types (useful for state machines):

TYPE state IS (idle, transmitting, receiving);
TYPE color IS (red, green, blue);

Arrays #

Arrays collect elements of the same type. The syntax for array declarations is:

TYPE type_name IS ARRAY (range_specs) OF element_type;

Examples:

TYPE byte_array IS ARRAY (0 TO 3) OF STD_LOGIC_VECTOR(7 DOWNTO 0);
TYPE matrix IS ARRAY (1 TO 3, 1 TO 4) OF BIT;

Arrays can be one-dimensional, two-dimensional, or multi-dimensional.

Array Slicing #

VHDL allows accessing portions of arrays through slicing:

signal x: BIT_VECTOR(7 DOWNTO 0) := "10101100";
-- Accessing a single bit
bit3 <= x(3);  -- Gets the 4th bit
-- Accessing a range
lower_bits <= x(3 DOWNTO 0);  -- Gets "1100"

However, there are limitations to slicing, especially with multi-dimensional arrays. Generally, slices of single elements or parts of single elements are always supported.

Records #

Records group elements of different types:

TYPE memory_access IS RECORD
    address: INTEGER RANGE 0 TO 255;
    data: STD_LOGIC_VECTOR(15 DOWNTO 0);
    read_write: BIT;
END RECORD;

Subtypes #

Subtypes are constrained versions of existing types:

SUBTYPE my_integer IS INTEGER RANGE -32 TO 32;
SUBTYPE my_logic IS STD_LOGIC RANGE '0' TO 'Z';

The advantage of subtypes is that operations between a subtype and its parent type are allowed, unlike between two distinct types.

Type Conversion #

Type conversion in VHDL falls into three categories:

  1. Automatic Conversion: Between types with the same base type.
  2. Type Casting: For compatible types (like STD_LOGIC_VECTOR and UNSIGNED).
  3. Type-Conversion Functions: Explicitly defined functions for converting between types.
-- Type casting
unsig <= UNSIGNED(slv);  -- STD_LOGIC_VECTOR to UNSIGNED
slv <= STD_LOGIC_VECTOR(unsig);  -- UNSIGNED to STD_LOGIC_VECTOR

-- Type-conversion functions
int_val <= TO_INTEGER(unsig);  -- UNSIGNED to INTEGER
slv <= TO_STDLOGICVECTOR(bv);  -- BIT_VECTOR to STD_LOGIC_VECTOR

Best Practices #

When working with VHDL data types:

  1. Use STD_LOGIC and STD_LOGIC_VECTOR for most designs (industry standard).
  2. Specify ranges for INTEGER types to avoid excessive bit usage.
  3. For arithmetic operations, explicitly convert between STD_LOGIC_VECTOR and UNSIGNED/SIGNED.
  4. Use the OTHERS keyword for easy initialization:
    signal data: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
  5. Be aware of type compatibility when assigning values or performing operations.

Conclusion #

Understanding VHDL data types is fundamental to effective hardware design. The right choice of data types makes your code clearer, more efficient, and closer to the actual hardware implementation. While there are many types to choose from, the most commonly used are STD_LOGIC_VECTOR for general connections, UNSIGNED/SIGNED for arithmetic, and enumerated types for state machines.

As you develop your VHDL skills, you’ll become more comfortable with choosing appropriate data types for each design situation, leading to more optimized and maintainable hardware descriptions.

Calendar April 20, 2025
Edit Edit this page